Answer by Peter Cordes for Concurrent stores seen in a consistent order
Intel CPUs (like all normal SMP systems) use (a variant of) MESI to ensure cache coherency for cached loads/stores. i.e. that all cores see the same view of memory through their caches.A core can only...
View ArticleAnswer by Benny for Concurrent stores seen in a consistent order
Ouch, this is a tough question! But I'll try...the writes go no deeper than L2Basically this is impossible since Intel uses inclusive caches. Any data written to L1, will also takes place in L2 and L3,...
View ArticleAnswer by Chamila Chulatunga for Concurrent stores seen in a consistent order
I believe what the Intel documentation is saying is that the mechanics of the x86 chip will ensure that the other processors always see the writes in a consistent order.So the other processors will...
View ArticleConcurrent stores seen in a consistent order
The Intel Architectures Software Developer's Manual, Aug. 2012, vol. 3A, sect. 8.2.2:Any two stores are seen in a consistent order by processors other than those performing the stores.But can this be...
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